1. Field of the Invention
The present invention relates to the field of physical design and, more particularly, to predicting upper-bound performance of a placed circuit design.
2. Description of the Related Art
Software based logic simulation and design tools presently are capable of performing functional and timing simulations for digital electronic designs which are written in a hardware description language such as Very High Speed Hardware Description Language (VHDL) or Verilog. Hardware description languages permit hardware designers to define signals at a very high level of abstraction. Logic design tools, referred to as electronic design automation or computer design automation tools (design tools), can specify circuit component placement as well as signal routing between placed components for a given circuit design. The abstracted signal representations can be translated to actual pins and circuitry on a microchip using any of a variety of commercially available fabrication and/or design tools.
One of the crucial tasks in the flow of implementing a design from a high level language like VHDL to actual layout is placement. Placement essentially assigns coordinate locations in an abstract grid to the blocks or components and the pins of the components. The objective of the placement phase, which can be performed by a design tool or a design tool component referred to as a placer, is to assign locations such that signals can be routed using minimal resources and/or with minimal delay governed by the design constraints.
A routing tool or routing tool component can follow the placer in the implementation flow. Given a set of pin locations, the router connects the signals together such that the design constraints are met. Generally, two modes of routing can be performed—a “resource” mode routing or a “delay” mode routing. In resource mode, signals are routed using a minimum number of resources. In contrast, delay mode routing routes a connection of a signal such that the route with minimal delay is attained for that connection. Since delay mode routing optimizes delay, a connection routed in delay mode cannot be further optimized in terms of signal propagation delay.
A useful metric within the context of design tools and circuit designs in general is an upper-bound determination of the achievable performance of a placed circuit design. The upper-bound provides an indication of the achievable performance for a given, placed circuit design in terms of the highest attainable clock frequency of the placed circuit design, or a portion thereof. The performance of a placed circuit design, or of a particular segment or clock domain, is dictated by the time required for a signal to propagate though a path, or from a driver register to a load register. Signals must propagate from one clocked register to the next in a time which is less than the period of the clock frequency that governs the driver and load registers of that path. Thus, the performance for a given, placed circuit design, or segment thereof, is defined by the path requiring the most time for a signal to propagate from one clocked node to another.
In the absence of a practical and efficient manner of estimating upper-bound performance, estimating the performance of a placed circuit design requires the design tool to actually determine connection routings of the placed circuit design and then analyze the various path delays of the routed design. Accordingly, a designer's options have been limited to allowing the design tool to complete the delay-aware routing process to route every connection of the placed circuit design in delay mode. As modern circuit designs, such as Field Programmable Gate Array (FPGA) designs, can include millions of timing paths and wires and hundreds of thousands of signals, investigating all routing options and evaluating placed circuit design timing can be run time expensive in terms of both the time and computing resources required. This option is not always feasible in light of modern expedited design cycles. In consequence, circuit designers frequently must proceed with circuit design without any such estimate of an upper-bound of placed circuit performance.
What is needed is a technique for predicting a realistic upper-bound on the performance of a placed circuit design which can be performed in a minimal amount of time and, further, provides a generalized solution which can be applied to any of a variety of different placed circuit designs.